Frequency synthesizers are used in virtually all wireless devices to create the fundamental frequency at which the wireless device operates. One type of frequency synthesizer is a fractional synthesizer. Many approaches to fractional synthesizers have been developed. A conventional fractional-N synthesizer is disclosed in U.S. Pat. No. 4,965,531. The fractional-N synthesizer of the '531 patent includes a phase frequency detector (PFD), a charge pump, a loop filter, a voltage controlled oscillator (VCO), a reference source, a fractional divider and a sigma delta modulator. The sigma delta modulator generates a sequence of integer numbers which control the divider and, on average, produces the fractional division of the VCO output signal to the PFD.
A problem with typical fractional-N synthesizers such as the synthesizer of the '521 patent is that the modulator creates high energy in fractional switching noise which peaks at one half the rate of the reference frequency provided to the phase detector.
If the frequency divider, phase detector and charge pump were ideal then the folding in the sampling process would fold the null at the PFD sample rate back on to the desired signal and no problem would result. The large fractional noise component would not fold onto the desired signal near zero.
If, however, non-linearities exist in the fractional divider, the phase detector or the charge pump, then harmonic content of the fractional noise may extend into the signal area at the PFD sample rate and would fold into the pass band of the output of the phase detector and charge pump. This is a major problem in fractional-N synthesizers and is a fundamental reason why the fractional-N synthesizer has higher noise than an integer N synthesizer.
Any non-linearity in the phase detector or charge pump in the fractional-N synthesizer will increase the noise floor of the synthesizer. It is known that a faster comparison rate at the phase detector will result in a lower noise integer synthesizer, but a faster comparison rate is problematic in a fractional synthesizer as the increase in speed of the comparison stresses the linearity of the phase detector. Also it is known that larger charge pump devices can lower the thermal noise contribution and 1/f noise contribution of the phase detector, but the larger devices have a difficult time to switch fast and have linearity problems in fractional synthesizers.
It is also known that unintended delay modulation in a fractional divider can cause unwanted noise and spurious. Although this is typically solved by retiming the leading edge of the fractional divider output to be fully synchronous with the input VCO phase for all divider settings, the fundamental signal may still suffer from amplitude modulation (AM).
There are many patents that attempt to address various issues related to problems with the spurious and phase noise of fractional synthesizers. U.S. Pat. No. 6,515,525 attempts to solve the problem with a complex error correction technique.
U.S. Pat. No. 5,055,800 discloses a fractional-N synthesizer that uses a complex multiplier, M, in the feedback loop to increase the fractional value to N/M. The synthesizer of the '800 patent filters the output of the multiplier with a band pass filter but ignores that the multiplier itself undesirably creates non-linearities which may cause harmonics of the fractional modulation spectra to fall in the low-noise regions near the desired signal. All of these references are incorporated herein by this reference.